1. Field of the Invention
The present invention relates to an operational amplifier circuit for CMOS input having an input voltage ranging from a negative power supply voltage to a positive power supply voltage.
2. Description of the Related Art
As a conventional CMOS operational amplifier circuit, there has been known a circuit illustrated in FIG. 4 (for example, see JP 2002-344261 A).
The operational amplifier circuit is roughly divided into two blocks consisting of a differential input circuit part 100 and a folded cascode circuit part 200.
First, the operation of the differential input circuit part 100 is described. A power supply voltage is applied between a VDD terminal and a VSS terminal. A differential input signal is supplied to an INP terminal and an INM terminal. An input differential pair of the differential input circuit part 100 includes n-type MOS transistors MN1 and MN2, and p-type MOS transistors MP1 and MP2. The input differential pair is thus configured, thereby enabling the operation in a wide input voltage range so that the p-type MOS transistor differential pair operates when the input voltage is low, and the n-type MOS transistor differential pair operates when the input voltage is high. That is, a voltage range of the differential input signal can be ensured from a negative power supply voltage (VSS) to a positive power supply voltage (VDD).
A MOS transistor MS1 is a MOS transistor for a current changeover circuit.
When the input voltage of the differential transistor pair is high and close to VDD, the MOS transistor MS1 is turned on. A current of a constant current source Ib1 flows in the n-type MOS transistors MN1 and MN2 by means of a current mirror circuit including a MOS transistor MS2 and a MOS transistor MS3. Accordingly, the n-type MOS transistor differential pair operates.
When the input voltage of the differential transistor pair is low and close to VSS, the MOS transistor MS1 is turned off. The current of the constant current source Ib1 flows in the p-type MOS transistors MP1 and MP2. Accordingly, the p-type MOS transistor differential pair operates.
Subsequently, the operation of the folded cascode circuit part 200 is described. The folded cascade circuit part 200 adds current signals from the p-type and n-type MOS transistor differential pairs of the differential input circuit part 100 together to output the added current signals to an output terminal OUT.
A voltage source Vb2 applies a cascode bias voltage to MOS transistors MP5 and MP6. For example, as illustrated in FIG. 5, a current is allowed to flow in a MOS transistor MB1 which is saturation-connected by a constant current source Ib4 to develop a voltage.
In general, a voltage Vgs between the gate and the source of the saturation-connected MOS transistor is represented by Expression (1).
                    Vgs        =                                                            2                ×                Id                            β                                +          Vt                                    (        1        )            where Id is a drain current of the MOS transistor (=constant current value of the constant current source Ib4), β is a parameter determined according to the process and the size of the MOS transistor, and Vt is a threshold voltage of the MOS transistor.
When the input voltage of the differential transistor pair of the differential input circuit part 100 is low and close to VSS, the current changeover MOS transistor MS1 is off, and hence no current flows in the n-type MOS transistors MN1 and MN2. In that state, currents of MOS transistors MP3 and MP4 in the folded cascode circuit are values obtained by subtracting a half current of the constant current source Ib1 from the currents of a constant current source Ib2 and a constant current source Ib3. The constant current source Ib2 and the constant current source Ib3 are so configured as to allow a current of the same current value IB2 to flow. When the current value of the constant current source Ib1 is IB1, the current values of the MOS transistors MP3 and MP4 are IB2−IB1/2.
On the other hand, when the input voltage of the differential transistor pair is high and close to VDD, the current changeover MOS transistor MS1 is on, and hence a current flows in the n-type MOS transistors MN1 and MN2. If the same current as the current value of the constant current source Ib1 flows in the MOS transistor MS3, current values of the MOS transistors MP3 and MP4 in the folded cascode circuit become IB2+IB1/2.
That is, the current values of the MOS transistors MP3 and MP4 change according to an input voltage.
A saturated voltage Vdsat of the MOS transistor is represented by Expression (2).
                    Vdsat        =                                            2              ×              Id                        β                                              (        2        )            where Id is a drain current of the MOS transistor, and β is a parameter determined according to the process and the size of the MOS transistor. As is apparent from Expression (2), when the current Id that flows in the MOS transistor changes, the saturated voltage Vdsat of the MOS transistor changes.
A cascode bias voltage is required to be set so that the drain-source voltages of the MOS transistors MP3, MP4, and MP5 become equal to or higher than the saturated voltage so as to prevent the MOS transistors MP3, MP4, and MP5 from falling within a unsaturated region.
In order to reduce the noise and the current consumption, the conventional CMOS operational amplifier circuit is required to reduce the currents of the constant current source Ib2 and the constant current source Ib3. In that case, the currents that flow in the MOS transistors MP3, MP4, and MP5 greatly change, that is, the fluctuation of the drain voltage becomes large according to the current from the differential input circuit part 100. Hence, the fear that the MOS transistors MP3 and MP5 fall within the unsaturated region becomes large, and therefore the gain of the amplifier is deteriorated.
That is, in the conventional CMOS operational amplifier circuit, it is difficult to design a circuit that operates with low noise, with low current consumption, and with stability.